AMD’s upcoming Zen 6 CPU family is set to use a blend of TSMC’s N3 and N2 process nodes, based on slide decks shared with engineers at three top motherboard makers. These plans outline five unique silicon lines, slated to launch late 2026 for servers, desktops, and notebooks. On the server side, the EPYC “Venice” lineup splits into Venice classic for everyday use and Venice dense for packed cloud setups. Both use a custom-tuned N2P process, promising an 8-10% clock-speed boost over the current N3E. Each classic die will pack 12 Zen 6 cores, while each dense die will hold 32 Zen 6c cores, allowing up to 256-core, 512-thread dense packages when eight dies connect via the existing organic interposer.
For client devices, AMD has picked codenames that give a clue about their purposes. “Olympic Ridge” will power the Ryzen 10000 desktop series using the N2P node, while “Gator Range” is aimed at gaming laptops over 55 W. The mainstream thin-and-light market gets “Medusa Point,” featuring a hybrid setup with an N2P compute tile and an N3P I/O tile, though entry-level models will stick to a cost-friendly monolithic N3P die. There’s also “Medusa Halo” and the budget-friendly “Bumblebee” series on the horizon, though their process choices are still being finalized. Thanks to tight collaboration between AMD and TSMC on metal layers and libraries, the final silicon will feel more like an “N2-AMD” setup than a typical N2P node. The first silicon is expected back from the fab before Christmas, with full production kicking off for the 2026 back-to-school notebook season and a later server update.
What do you think about these new Zen 6 plans? I’d love to hear your thoughts!
